The present invention relates to a ferroelectric memory device including memory cells each having a ferroelectric capacitor.
With the recent widespread use of small, high-performance electronic equipment provided with memory function, such as portable terminals and IC cards, demands for nonvolatile memories with low voltage, low power consumption, and high-speed operation suitable for such electronic equipment have increased. Flush memories are typical of non-volatile memories. From the standpoint of low power consumption and high-speed operation, however, ferroelectric memories have attracted attention. A ferroelectric memory stores non-volatile data utilizing the difference in the polarizing direction of a capacitor having a ferroelectric film. Accordingly, to rewrite data, only required is applying an electric field for inverting the polarizing direction. This has therefore features of low voltage, low power consumption, and high-speed operation.
A conventional configuration of memory cells constituting such a ferroelectric memory will be described with reference to FIGS. 21 through 23. FIG. 21 is an electric circuit diagram of a memory cell array of a conventional ferroelectric memory.
As shown in FIG. 21, the memory cell array of the conventional ferroelectric memory includes: a number of bit lines BL and a number of word lines WL extending to cross with each other; and a number of memory cells arranged in a matrix at positions corresponding to the respective crossings of the lines. Each memory cell includes: one memory cell transistor Q the gate electrode of which receives a signal from the word line WL; and one ferroelectric capacitor C interposed between the source region of the memory cell transistor Q and a cell plate line PL. FIG. 21 only illustrates four word lines WLa to WLd, four cell plate lines PLa to PLd, four bit lines BLa to BLd, and 16 sets of memory cell transistors Qaa to Qdd, and ferroelectric capacitors Caa to Cdd. It should be understood that the numbers of word lines and the like corresponding to the memory capacity (number of bits) of the ferroelectric memory are actually arranged. This also applies to FIGS. 22 and 23 to be described later.
The ferroelectric capacitor C includes a first electrode connected to the source region of the memory cell transistor and a second electrode connected to the cell plate line PL. This configuration will be described later in detail with reference to FIGS. 22 and 23. The memory cell structure of the ferroelectric memory strongly resembles the memory cell structure of a DRAM basically, but is different from that of the DRAM, which has a capacitor composed of a paraelectric, especially in that the ferroelectric capacitor C has a residual polarization characteristic (hysteresis characteristic) FIG. 24 is a view illustrating the residual polarization characteristic of a general ferroelectric capacitor C. The ferroelectric capacitor C generates positive residual polarization at point B or negative residual polarization at point D shown in FIG. 24, depending on the high/low relationship between the voltage applied to the first electrode of the ferroelectric capacitor C from the bit line BL via the memory cell transistor Q and the voltage applied to the second electrode of the ferroelectric capacitor C from the cell plate line PL.
For example, suppose it is defined during writing that the residual polarization is positive when the voltage applied to the first electrode of the ferroelectric capacitor C is a supply voltage VDD and the voltage applied to the second electrode thereof is a ground voltage,VSS (≈0), and that the residual polarization amount is L when the voltage applied to the first electrode of the ferroelectric capacitor C is the ground voltage VSS and the voltage applied to the second electrode thereof is the supply voltage VDD. During reading, when the potential at the ferroelectric capacitor C is read to the bit line BL by turning ON the memory cell transistor Q, the voltage at the bit line BL is high or low depending on whether the polarization of the ferroelectric capacitor C is positive or negative. The difference between the potential at the bit line and a reference potential is amplified by a sense amplifier (not shown), to allow the data to be determined xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In a one-transistor one-capacitor (1T1C) memory cell, one common reference cell is provided for a number of cells (for example, one for 256 cells), and a sense amplifier amplifies the difference between the reference potential read from the reference cell and each potential read to the bit line, to determine data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d depending on which potential is higher.
In a two-transistor two-capacitor (2T2C) memory cell, one memory cell is configured as follows. For example, in the structure shown in FIG. 21, one memory cell is composed of two transistors Qaa and Qba connected to one word line WLa and two bit lines BLa and BLb, and two ferroelectric capacitors Caa and Cba. Data xe2x80x9c1xe2x80x9d is allocated and stored when the polarization of the ferroelectric capacitor Caa is positive and the polarization of the ferroelectric capacitor Cba is negative, and data xe2x80x9c0xe2x80x9d is allocated and stored when the polarization of the ferroelectric capacitor Caa is negative and the polarization of the ferroelectric capacitor Cba is positive. During reading, the potential difference between the two bit lines BLa and BLb is amplified with a sense amplifier (not shown) provided between the two bit lines BLa and BLb. Data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is determined depending on which potential is higher.
The structure of the memory cell array of the ferroelectric memory on a semiconductor substrate will be described. FIG. 22 is a top view of the conventional ferroelectric memory where only the structure of the memory cell array located on a semiconductor substrate is illustrated and an interlayer insulating film is transparent.
As shown in FIGS. 22 and 23, active regions (source/drain regions, channel regions, and the like) of the transistors Q are formed in a semiconductor substrate 100. The word lines WL made of polysilicon, which serve as gate electrodes at positions above the channel regions, extend above the semiconductor substrate 100. Capacitance portions are formed above the respective source regions of the transistors Q. Each capacitance portion includes: a bottom electrode BE (first electrode) of the ferroelectric capacitor C, made of any of metals including metals of platinum and iridium group, which is an equivalent of a storage node of a DRAM; a ferroelectric film FD made of KNO3, PbLa2O3xe2x80x94ZrO2xe2x80x94TiO2 (PLZT), PbTiO3xe2x80x94PbZrO3 (PZT), or the like; and a top electrode TE (second electrode) made of any of metals including metals of platinum and iridium group. The bottom electrode BE of the capacitance portion is connected to the source of the memory cell transistor Q via a contact CS. This structure of the capacitance portion is called a stacked capacitor structure. The top electrodes TE constitute part of the cell plate lines PL that extend in parallel with the word lines WL as shown in FIG. 22. Above the capacitance portions, the bit lines BL extend in a direction parallel with the cross section of FIG. 23, and connected to the drain regions of the memory cell transistors Q via contacts CW. An interlayer insulating film 101 is formed over the semiconductor substrate 100 burying the contacts CS, the bottom electrodes BE, the ferroelectric films FD, the top electrodes TE (cell plate lines PL), the contacts CW, the bit lines BL, and the like. A LOCOS isolation insulation film electrically isolates every opposing source regions of adjacent memory cell transistors from each other. The portions other than the active regions enclosed by the rectangles in FIG. 22 represent the LOCOS isolation film.
Referring to FIGS. 21 through 23, in the memory cell array of the conventional ferroelectric memory, one cell plate line PL is provided for each word line WL. Such cell plate lines PL occupy a large area of the memory cell array as is apparent from FIG. 22. For separation of the cell plate lines of the adjacent memory cells from each other, it is required to secure a sufficiently wide gap between the cell plate lines. With this configuration, therefore, it is difficult to reduce the area occupied by the memory cell array.
Moreover, since the cell plate lines PL must be driven for operation, the speed of the device is disadvantageously lowered by a value corresponding to the time required for driving the cell plate lines.
In order to obviate the above two inconveniences, one common cell plate line PL may be provided for every two adjacent memory cells, in place of providing the cell plate line PL for every word line, and the voltage may be set at an intermediate potential. In other words, one cell plate line PL is provided for every two word lines WL, and the voltage at the cell plate line PL is fixed to (xc2xd) VDD, for example, during writing. By this setting, it is possible to generate positive residual polarization of the ferroelectric capacitor C when the voltage at the bit line BL is VDD and generate negative residual polarization of the ferroelectric capacitor C when the voltage at the bit line BL is the ground potential VSS (≈0). Thus, 1T1C or 2T2C memory cells can be formed as in the manner described above.
However, the above configuration has the following problem. The potential at the source region of a memory cell transistor is gradually closer to the ground voltage VSS due to junction leak. Therefore, if the potential at the cell plate line PL is kept fixed to the (xc2xd) VDD for a long period of time, polarization data at the ferroelectric capacitor may possibly be corrupted. To avoid this inconvenience, data may be refreshed, for example. However, refreshing causes other inconveniences of increasing powder consumption of the ferroelectric memory and complicating the control.
An object of the present invention is providing a ferroelectric memory device allowing for high-speed operation and reduced power consumption without causing inconveniences as described above by adopting measures for eliminating the necessity of driving cell plate lines.
The ferroelectric memory device of the present invention includes: a plurality of word lines; a plurality of bit lines crossing with the plurality of word lines; memory cells arranged in a matrix at respective crossings of the plurality of word lines and the plurality bit lines; at least one ferroelectric capacitor formed in each of the memory cells, the ferroelectric capacitor including a ferroelectric film and first and second electrodes sandwiching the ferroelectric film; at least one memory cell transistor formed in each of the memory cells, the memory cell transistor being interposed between the bit line and the first electrode of the ferroelectric capacitor, a gate of the memory cell transistor being connected to the word line; cell plate lines connected to the second electrodes of the ferroelectric capacitors; reset voltage supply lines for supplying a voltage having a potential substantially identical to the potential at the cell plate lines; reset transistors formed of switching transistors each interposed between the reset voltage supply line and the first electrode of the ferroelectric capacitor; and reset control signal lines for controlling ON/OFF of the reset transistors.
With the above configuration, data writing and reading can be done without the necessity of controlling the switch of the potential at the cell plate line between the ground potential and the supply potential as in the conventional ferroelectric memory device. In addition, the potentials at the first and second electrodes can be controlled to be substantially identical to each other by use of the reset transistor. This prevents data corruption caused by the first electrode being floated for a long period of time, without the necessity of refreshing.
In the above ferroelectric memory device, the memory cell may include each two of the memory cell transistors and the ferroelectric capacitors, establishing the 2T2C memory cell structure. In this case, also, one reset transistor is required for each of the ferroelectric capacitors.
In the above ferroelectric memory device, when the amplitude of a voltage at the bit lines is between a supply potential and a ground potential, the cell plate lines preferably supply an intermediate potential between the supply potential and the ground potential.
In the above ferroelectric memory device, the reset transistors may be configured to be ON during a standby period. With this configuration, during the standby period, a voltage signal from the reset voltage supply line is applied to the first electrodes of the ferroelectric capacitors. This ensures prevention of data corruption caused by the first electrodes of the ferroelectric capacitors being floated for a long period of time.
In the above ferroelectric memory device, the ferroelectric capacitor may be of a stacked structure where the first electrode is formed below the second electrode. With this structure, the second electrodes serving as the cell plate lines may be the top electrodes, and thus it is easy to realize the structure where the adjacent memory cells share the top electrodes (cell plate lines).
In the ferroelectric memory device, the reset transistor and the memory cell transistor may share one of diffusion layers. This further reduces the occupation area of the memory cell array.
In the ferroelectric memory device, the reset voltage supply line is formed of a conductive layer including a diffusion layer. This further reduces the occupation area of the memory cell array.
In the above ferroelectric memory device, the reset voltage supply line may include a backing line layer connected to a diffusion layer. This reduces the resistance and thus enhances the speed of the operation of memory cells.
In particular, the backing line layer is preferably made of the same metal material as the first electrodes of the ferroelectric capacitors.
In the above ferroelectric memory device, the reset transistor for switching the connection between the first electrode of the ferroelectric capacitor of one of two adjacent memory cells and the reset voltage supply line is interposed between the memory cell transistors of the two memory cells, and shares diffusion layers with the memory cell transistors on both sides, and the other reset transistor for switching the connection between the first electrode of the ferroelectric capacitor of the other of the two adjacent memory cells and the reset voltage supply line is formed so as to share diffusion layers with two memory cell transistors adjacent along the word line. This greatly reduces the occupation area of the memory cell array.
In the above configuration, the reset control signal line serving as gate electrodes of the reset transistors may have protrusions branching on one side at positions between the bit lines to serve as gate electrodes of the other reset transistors. In this case, it is possible to increase the proportion of the portions of the reset control signal lines that can be formed above the isolation insulation film. This reduces the parasitic capacitance and thus enhances the operation speed of the reset transistors.
The reset control signal line serving as gate electrodes of the reset transistors may have protrusions branching on alternate sides at positions between the bit lines to serve as gate electrodes of the other reset transistors. In this case, it is possible to provide the memory cell structures of the same geometry, and thus suppress a variation in geometry during the fabrication process.
The reset control signal line serving as gate electrodes of the reset transistors may have protrusions branching on both sides at positions between the bit lines to serve as gate electrodes of the other reset transistors. In this case, the reset control signal lines can be linear. This reduces the resistance of the reset control signal lines and thus enhances the operation speed of the reset transistors.
In the ferroelectric memory device, the bit lines may constitute bit pairs each composed of a first bit line and a second bit line formed with a sense amplifier therebetween, and memory cells among the plurality of memory cells connected to a common bit line may belong to either a first memory cell group connected to the first bit line or a second memory cell group connected to the second bit line. With this configuration, it is possible to arrange the memory cells into various patterns, to adopt a configuration suitable for the 1T1C memory cell structure.
As an example, each of the memory cells may include one memory cell transistor and one ferroelectric capacitor, the memory cell transistors of two adjacent memory cells among the plurality of memory cells may share one diffusion layer, and the memory cells may be divided into the first memory cell groups connected to the first bit lines and the second memory cell groups connected to the second bit lines every two adjacent memory cells, resulting in the first memory cell groups and the second memory cell groups being arranged in a zigzag fashion on the plane, that is, a so-called folded bit line structure.
The formation of the reset transistors provides effects as follows also for the devices in which the potential at the cell plate lines is switched between the ground potential and the supply potential. For example, when a certain memory cell is selected, no electric field is preferably applied between the electrodes of the ferroelectric capacitors of non-selected memory cells. However, there may sometimes arise the case that a potential difference is generated in ground potential at portions in the memory cell due to noise caused by an operating current for operation of the transistor connected to the electrode of the ferroelectric capacitor. Specifically, a difference may be generated between a substrate potential at a portion near a memory cell or the ground potential at the storage node and the ground potential at a portion near a drive circuit for driving the cell plate for the memory cell. This potential difference is applied to the capacitor, and this reduces the polarization of the capacitor and thus deteriorates the data retaining characteristic. According to the present invention, the reset transistor is controlled to be ON during the standby period. This prevents such a potential difference due to noise from being applied between the two electrodes of the ferroelectric capacitor, and thus the data retaining characteristic enhances. In particular, a large current flows in a cell plate line drive circuit portion connected to a selected memory cell for control of switching of the potential at the cell plate line. This may cause noise and possibly adversely influence the surrounding memory cells including the adjacent memory cells of the selected memory cell. According to the present invention, this adverse influence of noise can be suppressed.
The amplitude of the bit lines may be between a supply potential and a ground potential, the amplitude of the cell plate line for a selected memory cell among the memory cells may be between the supply potential and the ground potential, and the reset control signal lines may control the reset transistors of non-selected memory cells among the memory cells to be ON.
The ferroelectric memory device of the present invention allows for control of, for example, turning OFF the reset transistor after the rising of the word line. This control provides an effect of reducing the influence due to noise at the rising of the word line. Likewise, control may be done, so that the reset transistor is turned ON before the falling of the word line. This reduces the influence due to noise at the falling of the word line. This effect is obtainable both for the ferroelectric memory device configured not to vary (to fix) the potential at the cell plate lines and the ferroelectric memory device configured to vary the potential at the cell plate lines.
After the first electrode of the ferroelectric capacitor is isolated from the bit line, it may be reset by the reset transistor. This allows for resetting without influence of noise from the bit line, or resetting at high speed in the case where the capacitance of the ferroelectric capacitor is small. This effect is also obtainable both for the ferroelectric memory device configured not to vary (to fix) the potential at the cell plate lines and the ferroelectric memory device configured to vary the potential at the cell plate lines.